A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode for accumulating photo-generated charge in a specified portion of a substrate. Each pixel cell has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some imager circuits, each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo-charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
With reference to FIGS. 1, 2 and 3, which respectively illustrate a top-down view, a partial cross-sectional view and electrical circuit schematic of a conventional four transistor (4T) CMOS pixel sensor cell 100. When incident light 187 strikes the surface of a photosensor (photodiode) 120, electron/hole pairs are generated in the p-n junction of the photosensor (represented at the boundary of n-type accumulation region 122 and p-type surface layer 123 (FIG. 2)). The generated electrons (photo-charges) are collected in the n-type accumulation region 122 of the photosensor 120. The photo-charges move from the initial charge accumulation region 122 to a floating diffusion region 110 via a transfer transistor 106. The charge at the floating diffusion region 110 is typically converted to a pixel output voltage by a source follower transistor 108 which is output on a column output line 111 via a row select transistor 109.
Conventional CMOS imager designs, such as that shown in FIGS. 1–3 for pixel cell 100, provide only approximately a fifty percent fill factor, meaning only half of the pixel cell 100 is utilized in converting light to charge carriers. As shown, only a small portion of the cell 100 comprises a photosensor 120. The remainder of the pixel cell 100 includes isolation regions 102, shown as STI regions in a substrate 101, the floating diffusion region 110 coupled to a transfer transistor gate 106′ of the transfer transistor 106, and source/drain regions 115 for reset 107, source follower 108, and row select 109 transistors having respective gates 107′, 108′, and 109′. Moreover, as the total pixel area continues to decrease (due to desired scaling), it becomes increasingly important to create high sensitivity photosensors that utilize a minimum amount of surface area or to find more efficient layouts on the pixel array for the non-photosensitive components of the pixel cells to provide increased photosensitive areas.
FIG. 4 illustrates in electrical schematic form a six transistor (6T) pixel cell having a storage transistor 130 and associated storage gate 130′. Storage transistors 130 having storage gates 130′ and associated storage regions may be desirably used for various purposes, such as a frame shutter or to increase the charge capacity of the pixels. In addition, pixel cells also may include an anti-blooming transistor 140 having an associated gate 140′ to prevent charge overflow from a charge saturated photosensor 120. However, when additional transistors, such as a storage transistor 130 and/or anti-blooming transistor 140 are added to the pixel cell, the photosensor fill factor in further decreased.
Accordingly, there is a desire for a pixel cell, which includes storage transistors and/or anti-blooming transistors with associated gates, while having an efficient layout to permit a high fill factor.